Job Description

Contribute actively to creation and finalizing of the System Architecture by providing timely inputs

Develop behavioral models using System Verilog to accurately depict analog behavior in Mixed Signal Design environment

Setup necessary flows and verification environment based on understanding of System Architecture

Develop Sequences, Drivers, Monitors and Scoreboards in UVM

Simplify AMS models and replace with System Verilog constructs/models wherever possible to avoid long simulation runs

Implement scoreboards to enable self-testing in test benches to automate regressions at sub-system(circuits) as well chip level for mixed signal products

Study and learn the circuit design in detail.

Understand the functionality and timing requirements of the circuitry.

Develop patterns and regressions to increase the function coverage for all DC-DC voltage regulator architectures and features.

Provide support to design engineers, debug failures, handle bug tracking, and close coverage.

Develop and maintain test benches and test vectors using digital and analog simulation tools.

Create verification plan from functionality specification and in coordination with architects.

Work with cross-functional group to define and develop DFT patterns.